Non-volatile memory (NVM) is a memory device that retains content stored therein even when power is removed. EEPROM and flash memory are two commonly used non-volatile memory devices. In particular, flash memory has become widely used in electronic devices, especially portable electronic devices, because of its ability to provide data storage at low power levels. Modern day flash memory devices are typically implemented using a floating gate MOS transistor device as the memory cells. A floating gate MOS transistor device includes a floating gate that is formed between a control gate and the channel region (the substrate) of the MOS device and at least partially vertically aligned with the control gate. Charge storage on the floating gate determines the stored data state (“0” or “1”) of the memory cell.
The operation of the NVM memory device typically requires specified and stable reference voltage or current to ensure proper circuit operation. Due to fabrication process variations, the voltage or current values generated by the internal or on-chip reference sources often vary from chip to chip. To set the desired operating point for an internal reference source, adjustments to the integrated circuit are performed to fine tune the internal reference source to the desired operating point. The adjustment process is referred to as trimming and the adjustments are typically made through trim bits that are stored on the NVM memory device to set the desired operating point of the internal reference sources.
In NVM memory device, trimming is used not only to adjust internal analog voltage/current levels to the target levels but may also be used for compensating for temperature coefficient, or to enable/disable special internal features. In order to conserve silicon real estate, an NVM memory device often includes a dedicated area of the memory array for storing the trim data. Upon powering up of the NVM memory device, the trim data are read out as in a normal memory read operation and applied to the respective circuitry of the memory device. However, in some cases, it may not be possible to read out correctly the trim data from the NVM memory array upon power-up and before adjustments of the analog levels can be applied.